ASIC Verification Engineer-Rozwiń lokalizacje...
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Your responsibilities, Develop, maintain, and optimize SystemVerilog / UVM-based verification environments, Define and execute verification plans, test strategies, and coverage models, Implement constrained-random testbenches and functional.. więcej...
2026-05-20 08:40:44Umowa o pracęRodzaj pracy: Stała
VTOOL POLAND sp. z o.o19 dni temu z pracuj.pl